Conventional complementary metal oxide semiconductor (CMOS) process flows typically employ reactive ion etching (RIE) or a wet chemical etch for shallow trench isolation (STI) recess. However, with advanced non-planar technologies such as vertical field effect transistor (VFET) devices, STI recess can rarely be conducted by RIE or a wet chemical etch due to the poor etch selectivity (hardmask erosion) and/or etch loading effects. Etch loading effects refer to the etch rate dependence on a quantity of material being removed. With iso-dense loading, etch loading effects can undesirably lead to etch non-uniformity across a chip.
Thus, in order to compensate the etch loading effect, the current VFET process flow employs buffered hydrofluoric acid (BHF) plus chemical oxide removal (COR) for STI recess. Namely, with BHF the dense areas etch faster and the isolated areas etch slower. Conversely, with COR the dense areas etch slower and the isolated areas etch faster.
The current COR process, however, does not provide good etch selectivity to hardmask materials such as silicon nitride (SiN). Thus, the COR budget is limited in order to avoid aggressive hardmask erosion.
Accordingly, improved techniques for STI recess on VFET devices would be desirable.